Techniques for thickness measurements of patterned structures have been developed. The term “patterned structure” used herein, signifies a structure formed with regions having different optical properties with respect to an incident radiation. More particularly, a patterned structure represents a grid having one or more cycles, each cycle being formed of at least two different locally adjacent stacks. Each stack is comprised of layers having different optical properties.
Production of integrated circuits on semiconductor wafers requires maintaining tight control over the dimensions of small structures. Certain measuring techniques enable the local dimensions of a wafer to be measured with relatively high resolution, but at the expense of discontinued use of the wafer in production. For example, inspection using a scanning electron microscope gives measurements of the parameters of a patterned structure, but at the expense of cleaving it and thus excluding it from continued processing. Mass production of patterned structures such as wafers requires a non-destructive process for controlling thin film parameters in a manner enabling the local measurements to be performed.
One kind of the conventional techniques for measuring thickness of thin films is disclosed in U.S. Pat. No. 4,999,014. The technique is based on the use of small spot size and large numerical aperture for measurements on small areas. Unfortunately, in the case of a very small structure, this approach suffers from a common drawback associated, on the one hand, with the use of a small spot-size and, on the other hand, owing to the large numerical aperture, with the collection of high diffraction orders. The term “small spot-size” signifies the spot diameter similar in size to the line or space width of the measured structure, i.e. a single grid cycle. This leads to various problems, which are difficult to solve. Indeed, not all the stacks' layers are in the focus of an optical system used for collecting reflected light, the optical system being bulky and complicated. Detected signals are sensitive to small details of a grid profile and to small deviations in the spot placement. Diffraction effects, which depend significantly on the grid profile and topography and therefore are difficult to model, have to be included in calculations.
Another example of the conventional techniques of the kind specified is disclosed in U.S. Pat. No. 5,361,137 and relates to a method and an apparatus for measuring the submicron linewidths of a patterned structure. The measurements are performed on a so-called “test pattern” in the form of a diffraction grating, which is placed in a test area of the wafer. Here, as in most conventional systems, a monochromatic incident light is employed and diffraction patterns are produced and analyzed. However, a large number of test areas are used and also information on multiple parameters cannot be obtained.
According to some conventional techniques, for example that disclosed in U.S. Pat. No. 5,087,121, portions with and without trenches are separately illuminated with broadband light, the reflection spectrum is measured and corresponding results are compared to each other with the result being the height or depth of a structure. However, it is often the case that the structure under inspection is such that the different portions cannot be separately imaged. This is owing to an unavoidable limitation associated with the diameter of a beam of incident radiation striking the structure.
The above approach utilizes frequency filtering to enable separation of interference signals from different layers. This is not feasible for layers of small thickness and small thickness difference because of a limited number of reflection oscillations.
Yet another example of the conventional technique for implementing depth measurements is disclosed in U.S. Pat. No. 5,702,956. The method is based on the use of a test site that represents a patterned structure similar to that of the wafer (circuit site), but taken in an enlarged scale. The test site is in the form of a plurality of test areas each located in the space between two locally adjacent circuit areas. The test areas are designed so as to be large enough to have a trench depth measured by an in-line measuring tool. The measurements are performed by comparing the parameters of different test areas assuming that the process is independent of feature size. For many processes in the field such as etching and photoresist development, this assumption is incorrect and this method is therefor inapplicable.